1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, it relates to a layout of sense amplifier (S/A) drive signal lines and column selection lines in a large capacity memory such as a 16 M-bit dynamic random access memory (DRAM).
2. Description of the Related Art
Semiconductor memory devices are generally constituted in the form of a semiconductor chip which typically has a rectangular form. In this regard, it is necessary to devise a configuration of layout of a S/A drive circuit from which S/A drive signal lines are led out, and a column decoder from which column selection lines are led out, according to a memory capacity. Especially, since the S/A drive signal lines carry a large amount of current for driving sense amplifiers, wiring widths thereof must be selected to be sufficiently wide.
In view of this, it is desirable to provide the S/A drive circuit in a periphery of a longer side of the semiconductor chip and accordingly arrange the S/A drive signal lines along a direction parallel to a direction of a shorter side thereof. Such a configuration of layout is suitable for a relatively small capacity memory such as a 4 M-bit DRAM.
However, the above configuration of layout is not suitable for a relatively large capacity memory such as a 16 M-bit DRAM which has been recently developed. This is because the S/A drive circuit needs a considerable large area on the chip and thus it is very difficult to arrange the S/A drive circuit in the periphery of the longer side of the semiconductor chip, from a viewpoint of the layout.
Note, the problems in the prior art will be explained later in detail in contrast with the preferred embodiments of the present invention.